Senior Principal SoC IP Design Verification Engineer

3 weeks ago

Cork, Cork, Ireland Software Placements Full time
Senior Principal SoC IP Design Verification Engineer

Our client, a leading Multinational Semiconductor Company, requires a Senior Principal Digital Design SoC IP Verification Engineer for a role based in Cork City, Ireland.

Role:

The group you will be joining develops and licenses IP for system designs. This includes CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems. This group requires an experienced, motivated Verification Engineer to join a new team. You will join a team implementing reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high-performance applications. The group will also develop software and applications for reference systems and product demonstrations, highlighting the capability of subsystems and components.

Responsibilities:

  • Design, develop and debug SoC reference systems.
  • Develop tests, scoreboards, checkers, coverage, etc. to verify subsystems.
  • Integrate compute, memory, and interface IP in system designs.
  • Analyse IP products and implementation flows.
  • Identify gaps and work with development teams to improve products.
  • Develop collateral and training material for system customers.
  • Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.
  • Stay up to date with the latest industry trends, technologies, and design methodologies, and incorporate them into the team's workflows.

Experience:

  • BS in Electronic Engineering/Computer Science with 15+ years of work experience, or MS in EE/CS with 8+ years of experience.
  • Must have at least 4 years of experience in ASIC design, integration, or verification teams.
  • Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.
  • Expertise in Verilog/System Verilog for coding and verification.
  • Proficiency in RTL design techniques, including synthesis, timing closure, and verification.
  • Experience in using UVM for functional verification of ASIC designs.
  • Experience with EDA tools like Cadence and Synopsys for design simulation and verification.
  • Extensive experience with FPGA emulation, design tools, and verification.

Contact:

For further information, please contact Mícheál at Software Placements on 00353 1 5254642 or email micheal@softwareplacements.ie

Seniority level
  • Mid-Senior level
Employment type
  • Full-time
Job function
  • Engineering and Design
Industries
  • Semiconductor Manufacturing and Appliances, Electrical, and Electronics Manufacturing
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