Staff Mixed-Signal Dv Engineer

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Staff Mixed-Signal DV Engineer, Limerick
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Client:
Location:
Limerick, Ireland
Job Category:
Other
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EU work permit required:
Yes
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Job Reference:
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Job Views:
4
Posted:
Expiry Date:
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Job Description:
About Analog Devices
Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible.
Learn more atand onand.
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company.
This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office.
SVV is building out an Incubation DV Services team that'll serve various BUs across ADI ensuring elimination of unplanned silicon iterations by boosting DV quality and embedding best practices within BUs.
We're seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for large, mixed-signal chips from scratch.
Additionally, SVV is also responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
About the role
In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation and release of products to customers.
They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products.
This is a senior role with the opportunity to create real impact within the organization and build a promising career.
Responsibilities
Verification of complex mixed signal designs and sub-systems using leading edge verification methodologies.
Architecting a unified verification testbench environment supporting both digital only and mixed signal verification requirements (UVM based)
Defining testplans, tests and verification methodology for chip-level verification.
Working with the design team in generating test-plans and closure of code and functional coverage
Continuous interaction with analog mixed signal and firmware teams
Supporting post-silicon verification activities of the products working with design, product evaluation and applications engineering teams.
Tracking and management of design verification improvements
Internal and External customer interaction/management
Technically mentoring less-experienced verification engineers on SoC Verification responsible for block/IP-level DV
Minimum Qualifications
Bachelor's or Master's degree, in Engineering (Electronic Engineering) or equivalent.
10+ years ASIC design verification or related work experience.
Preferred Qualitifcations
Leadership skills enabling one to define, sell and implement a verification strategy
Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications
Proficient in developing unit and SoC level test benches using UVM
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology, formal verification
Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium
Knowledge of SystemVerilog, digital simulation and debug
Working with Cortex-M series based processors
Gate Level Simulation (GLS) verification flow for SoC verification.
Pre and post-silicon verification testflow including HW, SW and FW
RTL design/front-end design/FPGA flow experience
Experience in Matlab (including for co-simulation and HDL generation) and digital signal processing (e.g.development and verification for filters and Cordics)
Low power methodologies such as CPF/UPF
Functional Safety requirements
Excellent interpersonal and communication skills and the dream to take on diverse challenges
Self-motivated and enthusiastic
#LI-RW1
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
About Analog Devices
Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible.
Learn more atand onand.
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company.
This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office.
SVV is building out an Incubation DV Services team that'll serve various BUs across ADI ensuring elimination of unplanned silicon iterations by boosting DV quality and embedding best practices within BUs.
We're seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for large, mixed-signal chips from scratch.
Additionally, SVV is also responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.
About the role
In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation and release of products to customers.
They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products.
This is a senior role with the opportunity to create real impact within the organization and build a promising career.
Responsibilities
Verification of complex mixed signal designs and sub-systems using leading edge verification methodologies.
Architecting a unified verification testbench environment supporting both digital only and mixed signal verification requirements (UVM based)
Defining testplans, tests and verification methodology for chip-level verification.
Working with the design team in generating test-plans and closure of code and functional coverage
Continuous interaction with analog mixed signal and firmware teams
Supporting post-silicon verification activities of the products working with design, product evaluation and applications engineering teams.
Tracking and management of design verification improvements
Internal and External customer interaction/management
Technically mentoring less-experienced verification engineers on SoC Verification responsible for block/IP-level DV
Minimum Qualifications
Bachelor's or Master's degree, in Engineering (Electronic Engineering) or equivalent.
10+ years ASIC design verification or related work experience.
Preferred Qualitifcations
Leadership skills enabling one to define, sell and implement a verification strategy
Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications
Proficient in developing unit and SoC level test benches using UVM
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology, formal verification
Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium
Knowledge of SystemVerilog, digital simulation and debug
Working with Cortex-M series based processors
Gate Level Simulation (GLS) verification flow for SoC verification.
Pre and post-silicon verification testflow including HW, SW and FW
Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting
RTL design/front-end design/FPGA flow experience
Experience in Matlab (including for co-simulation and HDL generation) and digital signal processing (e.g.development and verification for filters and Cordics)
Low power methodologies such as CPF/UPF
Functional Safety requirements
Excellent interpersonal and communication skills and the dream to take on diverse challenges
Self-motivated and enthusiastic
#LI-RW1
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days #J-18808-Ljbffr