Staff/Snr Asic Design Verification Engineer

3 weeks ago

Cork, Cork, Ireland Software Placements Full time

Client:

Our client, a leading Multinational Semiconductor Telecom Company, requires Staff or Senior ASIC Design Verification Engineers with Sensors for roles based in Cork City, Ireland.

The position is technology-focused and involves participation in a broad range of sensors systems engineering activities within the Sensors Technologies group.
Role: You will be deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification, developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments, and verifying sensor algorithms RTL for ASIC tapeout quality delivery.

Responsibilities: Test plan development based on Design documents and interaction with design/systems engineers Implementing C model integration within UVM framework.
Writing SystemVerilog assertions Debugging, verifying, optimizing, and bit-exact matching with test vectors Analyzing coverage data and working with Design teams to address coverage holes Developing/augmenting framework for running regressions Debugging regression failures with design/Systems teams Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level Python automation for improving workflows and team efficiency Participate in all project reviews Supporting software and other teams with debug Documentation Education: Bachelor's degree in Science, Engineering, or related field.
Experience: 3+ years ASIC design verification, UVM-based functional verification, or related work experience.
Experience using formal verification tools like Jasper or VC_Formal is a plus Experience with SystemC and Matlab are a plus.
Gate level Simulation debug and usage of power extraction tools is a plus Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology Experienced with Assertions like System Verilog Assertions Experience with debugging test failures and reporting verification results to achieve the expected code/functional/line coverage goals Extensive usage of RTL simulation tools.
UVM, System Verilog, Perl/Python shell-scripting skills required Familiarity with C/C++ Strong analytical skills and ability to work in a dynamic and fast-paced team environment Excellent written and verbal skills Strong interpersonal skills and a good team player Working Model: The company offers a hybrid working model of 3 days onsite and 2 days from home.
Well-being and life balance are fundamental.
As such, company policy allows employees to blend short-term remote working with annual leave.
Contact:

For further information, please contact Mícheál at Software Placements on 00353 1 5254642 or email

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