Principal Verification Engineer

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Client: CADENCE IRELAND
Location: Dublin, Ireland
Job Category: Other
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EU work permit required: Yes
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Job Reference: 4012c46cc842
Job Views: 4
Posted: 03.06.2025
Expiry Date: 18.07.2025
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Job Description: At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise.
The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Principal Verification Engineer (SERDES) Locations: Cork Reports to: Group Director Job Overview: The Cadence Serdes PHY team based at our R&D center of excellence in Cork, is seeking ambitious analog designers who wish to work on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g.
3nm).

The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).

The Principal Verification Engineer will take a Technical Leadership role on the Verification team (Digital & AMS) as part of a SERDES Product Team located at Cork, Ireland.

Job Responsibilities: Verification of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g.
3nm FinFET CMOS) Specification, Design and Verification of High Speed PHY IP based on communication protocols (PCIe, Ethernet) Verification from initial concept/specification through final verification of conformance to customer specifications using Coverage metric Implementation, Tracking and Closure Prototyping, Emulation, Customer delivery and support Work with cross-functional teams ranging from architecture, all aspects of circuit design, Layout development, RTL design & Validation, Physical design & Test chip development Participate in technical leadership of the team in the areas of digital design and verification, SERDES architectures Work with global teams (US, west coast and east coast), which work in different time-zones Job Qualifications: BEng, MEng, PhD or equivalent Candidate's background should include a minimum of 7 years ofexperience in CMOS SERDES or high-speed I/O IC design and development Working knowledge of a set of common SERDES standards Wide experience with digital design and verification tools; RTL design using Verilog & verification with System Verilog and UVM Experience of Assertion Based Formal Verification essential Experience of Front-end design tools covering LINT, Synthesis & CDC Analysis Excellent problem-solving skills and ability to work cooperatively in a team environment Excellent communication and stakeholder management skills Additional Skills/Preferences: Prior experience with post Silicon validation & customer IP deployment of one or more Serial IO IPs/ complex Memory Interface IPs is an added advantage Knowledge of PCIe, CXL protocols preferred Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel: > 10%
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