ASIC Verification Engineer

3 weeks ago


Cork, Cork, Ireland European Tech Recruit Full time

3 days ago Be among the first 25 applicants

Direct message the job poster from European Tech Recruit

Senior Consultant | Semiconductor, Automotive, Software Engineering

An exciting career opportunity for an experienced ASIC Verification Engineer to join Global Leading Semiconductor Company, working alongside their exceptional team in Cork, Ireland.

The position is technology focused and involves participation in a broad range of sensors systems engineering activities within the Sensors Technologies group.

Responsibilities will include:

  • Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
  • Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.
  • Verifying sensor algorithms RTL for ASIC tapeout quality delivery
  • Test plan development based on Design documents and interaction with design/systems engineers
  • Implementing C model integration within UVM framework.
  • Debugging, verifying, optimizing, and bit-exact matching with test vectors
  • Analyzing coverage data and working with Design teams to address coverage holes
  • Develop/augment framework for running regressions
  • Debugging regression failures with design/Systems teams
  • Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level
  • Supporting software and other teams with debug
  • Documentation

Experience:

  • Bachelor's degree in Science, Engineering, or related field.
  • 4+ years ASIC design verification, UVM-based functional verification, or related work experience.
  • Experience using formal verification tools like Jasper or VC_Formal is a plus
  • Experience with SystemC and Matlab are a plus.
  • Gate level Simulation debug and usage of power extraction tools is a plus
  • Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
  • Experienced with Assertions like System Verilog Assertions
  • Experience with debugging test failures and report verification result to achieve the expected code/functional/line coverage goals
  • Extensive usage of RTL simulation tools.

By applying to this role, you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/wp-content/uploads/2020/04/Privacy-Notice.pdf).

Seniority level
  • Seniority levelMid-Senior level
Employment type
  • Employment typeFull-time
Job function
  • Job functionDesign, Engineering, and Information Technology
  • IndustriesSemiconductor Manufacturing, Computers and Electronics Manufacturing, and Computer Hardware Manufacturing

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