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Principal Analog Layout Engineer
4 weeks ago
Principal Analog Layout Engineer
We are seeking a Principal Analog Layout Engineer for our client Chipright, located in Galway, Ireland. The ideal candidate will have:
- Minimum 5 years of experience, preferably over 8+ years
- Experience with 65nm technology and below (ideally 22nm and below)
- Understanding of layout for critical timing components such as PLL, DLL, and clock distribution
- Knowledge of matching techniques for timing circuits and current cells
- Chip finishing experience is a bonus
- Experience with Cadence PVS/QRC/Pegasus tools
This position requires an EU work permit. The posting was made on 17.06.2025 and will expire on 01.08.2025. The job has been viewed 4 times.
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