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GPU Design Implementation Engineer
4 weeks ago
GPU Design Implementation Engineer
About the role
As a member of the Graphics team, the successful applicant will help integrate, implement, and develop state-of-the-art GPU cores and will work closely with the graphics microarchitecture and physical design teams. The candidate should have an in-depth understanding of ASIC design flow and the challenges posed by advanced deep sub-micron technologies.
The Design Implementation Engineer will manage all aspects of front-end implementation design challenges and methodologies within our GPU team. Responsibilities include working with execution-driven teams for tape-outs, supporting new methodologies and flows to improve QoR such as performance, power, and area.
Responsibilities
- RTL to GDS2 flow, tools, and methodologies such as synthesis, static timing analysis, formal verification, physical design, and ECO generation/verification.
- Implementation and delivery of GPU cores from RTL to GDSII.
- Identify areas for flow and process improvements.
- RTL synthesis using physically aware tools.
- Formal verification using industry-standard tools for RTL-netlist and netlist-netlist checks.
- Close design timing by running static timing analysis and developing constraints.
- Generate and verify ECOs for functional and timing fixes, collaborating with the physical design team.
- Implement low power synthesis flows for multiple corners.
Skills and Experience we would love to see
- Knowledge and experience in graphics design and development.
- Proficiency in Perl, TCL, and shell scripting.
- Hands-on experience with front-end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality, and Synopsys PrimeTime.
- Familiarity with the latest EDA tools for synthesis, logic equivalence checking, timing analysis, and physical design.
- Ability to problem-solve complex, detailed issues.
Minimum Qualifications
- Bachelor's degree in Engineering, Science, or a closely related field.
- At least 6 months of experience with digital design and RTL development.
- At least 6 months of experience with synthesis, static timing, timing closure, constraints, and formal verification.
For full details or to apply, contact me at ww@eu-recruit.com. We may collect and process your personal data as outlined in our Privacy Notice.
Additional Details- Seniority level: Mid-Senior level
- Employment type: Full-time
- Job function: Engineering and Design
- Industries: Semiconductor Manufacturing, Computer Hardware Manufacturing, Computers and Electronics Manufacturing