(Urgent) Sensor Subsystem Design Verification Engineer
2 days ago
Company:
QT Technologies Ireland Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
About the Role
Sensors-based technology has a wide range of applications including navigation, gaming, smart user interface, multimedia, virtual reality and augmented reality. This challenging position offers the opportunity to work with leading edge sensor technologies embedded in smartphones, automotive, IOT, smartwatches as well as other consumer electronics devices. Job activities span the ASIC design verification process from test planning, environment development using UVM, regressions, coverage analysis and meeting all Qualcomm quality metrics for tapeout.
You will work with architects of Systems, Design teams, as well as other SoC team verification engineers and software engineers to verify designs specific to Digital Sensor subsystems for integration into SoC for mobile applications.
Responsibilities will include:
- Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
- Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.
- Test plan development based on Design documents and interaction with design/systems engineers
- Writing and debugging SystemVerilog assertions
- Analysing coverage data and working with Design teams to address coverage holes
- Develop/augment framework for running regressions
- Running/Debugging Power aware simulations
- Debugging regression failures with design/Systems teams
- Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level
- Python/Perl automation for improving workflows and team efficiency
- Participate in all project reviews
- Supporting software and other teams with debug
- Documentation
What are we looking for?
- Bachelor's degree in Science, Engineering, or related field.
- ASIC design verification, UVM-based functional verification, or related work experience.
- Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology
- Experienced with System Verilog Assertions
- Experience with debugging test failures and report verification result to achieve the expected code/functional/line coverage goals
- Extensive usage of RTL simulation tools.
- Experience using formal verification tools like Jasper or VC_Formal
- UVM, System Verilog, Perl/Python shell-scripting skills required
- Familiarity with C/C++
- Strong analytical and multitasking skills and ability to work in a dynamic and fast paced team environment
- Excellent written and verbal skills
- Strong interpersonal skills and a good team player
- Strong technical leadership and coaching skills is a plus
Where you will be working
Cork has a proud reputation as Ireland's second largest economic engine and is now one of the Top 20 location choices in Europe with 39,000 people being employed by over 170 overseas companies. There's a growing diversity in the region with people from many nationalities relocating to Cork, relishing the opportunity to work and live in a location that offers an excellent quality of life. A gateway to Europe, Cork airport provides access to almost 50 international destinations including transatlantic air routes.
Equal Opportunities
We are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any protected classification.
What's on Offer
Apart from working in an open, relaxed and collaborative space, you will enjoy:
- Salary, stock and performance related bonus
- Maternity/Paternity Leave
- Employee stock purchase scheme
- Matching pension scheme
- Education Assistance
- Relocation and immigration support (if needed)
- Life, Medical, Income and Travel Insurance
- Subsidised memberships for physical and mental well-being
- Bicycle purchase scheme
- Employee run clubs, including, running, football, chess, badminton + many more
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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