ASIC Digital IP Design/Verification, Director

5 days ago

Dublin, Ireland Synopsys, Inc. Full time

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Main Responsibilities

Senior VLSI front end leader should lead a large team of IP design/verification activities. This challenging senior role combines technical expertise with leadership responsibilities in a multi-site environment, focusing on developing IP Cores for connectivity protocols in the Design and Verification domains.

Responsibilities extend to hiring, planning, and ensuring quality and schedule compliance. In addition to interacting with customers, the ideal candidate must be well-versed in ASIC design methodologies, verification strategies, and must possess the ability to interact with upper management confidently. This is an opportunity to thrive in a project and team-oriented global environment.

Desired background/qualifications

- Strong management background, including at least 10 years as an individual contributor in VSLI designs followed by people and project management responsibilities, with proven skills in leading large teams, setting up technical processes, customer interactions, project planning and tracking, managing deliveries, and working with remote teams.

- The ability to mentor and train junior engineers and possess outstanding problem-solving skills. Set up teams and increase them to sizes of 50+.

- Familiarity with protocols such as PCIe, MIPI‑UFS, Unipro, SD‑MMC, Ethernet, USB, and AMBA.

- Prior experience in design/verification includes working on IP Cores or SoC Designs for devices like Set Top Boxes, Mobile Handsets, and Smart Devices, Servers, Automotive as well as knowledge of protocols such as MIPI‑UFS/Unipro/SD‑MMC/Ethernet/USB/AMBA.

Design

- Prior hands-on experience in creating complex designs, particularly control path-oriented designs like asynchronous FIFO, DMA architectures, SPRAM/DPRAM interface design, and more.

- Proficiency in Verilog/System Verilog coding and Simulation tools is essential, along with knowledge of synthesis flow, static timing flows, formal checking, and experience with Perforce or a similar revision control environment. Exposure to quality processes in the context of IP design and verification is considered an added advantage.

Experience in Verification needed

- UVM/VMM/OVM/eRM-based verification methodologies

- Proficiency in creating test benches for complex designs, utilizing constrained random verification methods, test planning, and coverage management

- Hands-on experience with Verilog/System Verilog coding and simulation tools

- Familiarity with optimizing simulation runs, utilizing AI-based tools for failure categorization, and exposure to revision control environments like Perforce

- Exposure to quality processes for IP design and verification is a plus

- Excellent written and verbal communication abilities, be adept at conflict resolution, and maintain composure in high-pressure situations.

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