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Senior ASIC Design Verification Expert

3 weeks ago


Cork, Cork, Ireland beBeeVerification Full time

Job Title: Senior ASIC Design Verification Engineer

">About the Role

We are seeking a talented and experienced Senior ASIC Design Verification Engineer to join our team. As a key member of our engineering group, you will be responsible for defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development for high-performance, low-power products.

You will work closely with cross-functional teams to determine product execution paths and collaborate with architects, design teams, and software engineers to verify designs specific to Digital Sensor subsystems for integration into SoCs for mobile applications.

Key Responsibilities:

  • Deploy industry-leading verification methodologies such as UVM and Formal Verification
  • Develop testbenches and verification components such as UVCs, C models, and vertical/horizontal reusable verification environments
  • Test plan development based on design documents and interaction with design/systems engineers
  • Writing and debugging SystemVerilog assertions
  • Analyzing coverage data and working with design teams to address coverage holes
  • Developing/augmenting frameworks for running regressions
  • Running/debugging power-aware simulations
  • Debugging regression failures with design/systems teams
  • Supporting integration of designs in higher-level subsystems, including test planning, test vector delivery, and debug of test vectors at the integration level
  • Python/Perl automation for improving workflows and team efficiency
  • Participating in all project reviews
  • Supporting software and other teams with debug
Requirements

To be successful in this role, you will need:

  • Bachelor's degree in Science, Engineering, or related field, and 4+ years of ASIC design verification, UVM-based functional verification, or related work experience
  • Experience with constrained-random verification environments and flow build-up with UVM, Coverage-Driven verification methodology
  • Experience with SystemVerilog Assertions
  • Experience with debugging test failures and reporting verification results to achieve expected code/functional/line coverage goals
  • Extensive usage of RTL simulation tools
  • Experience using formal verification tools like Jasper or VC_Formal
  • UVM, SystemVerilog, Perl/Python shell-scripting skills required
  • Familiarity with C/C++
  • Strong analytical and multitasking skills, with ability to work in a dynamic and fast-paced team environment
  • Excellent written and verbal communication skills
  • Strong interpersonal skills and a good team player
  • Strong technical leadership and coaching skills (plus)
What We Offer

We offer a competitive salary, stock, and performance-related bonus, maternity/paternity leave, employee stock purchase scheme, matching pension scheme, education assistance, relocation and immigration support, life, medical, income, and travel insurance, subsidized memberships for physical and mental well-being, bicycle purchase scheme, and employee-run clubs.

We are an equal opportunities employer and welcome applications from candidates with equivalent experience who can demonstrate an ability to fulfill the principal duties of the role and possess the required competencies.

Please note that Qualcomm is committed to providing reasonable accommodations to support individuals with disabilities to participate in the hiring process.

Contact Qualcomm Careers for more information about this role.