
Senior Digital Verification Specialist
2 weeks ago
Job Overview
We are seeking an experienced digital verification specialist to join our team. As a key member of the team, you will work on the development of System Verilog – UVM testbenches and be responsible for solving complex problems related to test bench development.
Key Responsibilities:
- Develop System Verilog – UVM testbenches to ensure accurate and efficient verification.
- Design and implement UVC components from scratch for new verification environments.
- Create functional coverage models to measure and improve testbench effectiveness.
- Debug failing test cases to ensure test benches meet quality and completeness standards.
- Participate in reviews to ensure test benches meet quality and completeness standards.
- Contribute to verification perspectives in design and concept meetings.
- Ensure test benches meet sign-off targets and drive efficiency in verification activities.
Required Skills and Qualifications:
- At least 8 years of experience in verification working with Verilog and/or SystemVerilog.
- 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform.
- Ability to understand complex design specifications and derive features and test bench architectures.
- Familiarity with CAD/EDA tools for design and simulation.
- Working knowledge in scripting languages for verification environments (Python, Perl, TCL preferred).
- Strong background in digital logic design and verification.
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