
High-Performance Verification Specialist
2 weeks ago
As a senior verification engineer, you will collaborate with the architecture and design team to develop thorough verification plans, create detailed test plan documents, and integrate third-party verification IPs/units.
You will be responsible for crafting a constraint random verification environment using System Verilog and UVM, conducting power-aware verification in a random environment with embedded firmware running on the design, and regressing and closing necessary low-power coverage metrics to ensure high-quality designs.
- Create advanced verification components and testbenches for low-power verification.
- Work closely with tool vendors to enhance verification flows.
- Perform in-depth failure debugging involving hardware-software co-debugging.
- Develop portable test setups and verification components that can be reused across simulation and emulation platforms.
- Support SoC digital validation for integration verification, chip bring-up, and post-silicon debugging.
Key Requirements:
- At least 3 years of hands-on experience in System Verilog, OVM/UVM-based constrained random verification.
- At least 3 years in design validation/post-silicon debugging.
- Proficiency in low-power SoC design constructs such as clock gates, level shifters, isolation cells, and state retention cells.
Desirable Skills:
- Master's degree in Electrical Engineering or equivalent; 8 years of practical experience.
- Experience with Synopsys NLP (native Low Power) tool.
- Working knowledge of GLS, PAGLS, and scripting languages such as Perl and Python.
The company offers a hybrid working model, allowing employees to balance remote work with annual leave.
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