Senior GPU Power Design Engineer

1 week ago

Cork, Cork, Ireland beBeeVerification Full time €80,000 - €120,000

Are you looking for a challenging role in the field of GPU Power Design Verification? We are seeking an experienced Senior GPU Power Design Verification Engineer to join our team.

The ideal candidate will have a strong background in system verilog, OVM/UVM based constrained random verification, and experience with developing verification components/UVCs and testbenches for RTL verification. They will also be proficient in low power SoC design constructs such as clock gates, level shifters, isolation cells, and state retention cells.

Key responsibilities include working with the Architecture and Design team to understand low power design features, create verification plans, develop test plan documents, and get them reviewed. The engineer will also develop verification components and testbenches for low power verification, integrate third-party VIPs/UVCs as required, and create constraint random verification environments using System Verilog and UVM.

The successful candidate will have 3+ years of hands-on experience in system verilog, OVM/UVM based constrained random verification, and 3+ years in design validation/post-silicon debug. They will also have experience with UPF based Power Aware verification, functional coverage model development, and code coverage closure.

Desirable skills include proficiency in scripting languages such as Perl and Python, and experience with Synopsys NLP (native Low Power) tool. Knowledge of GLS, PAGLS, and power aware emulation verification is also beneficial.

This is a great opportunity for a motivated individual to take their career to the next level. If you are passionate about GPU Power Design Verification and have the necessary skills and experience, we encourage you to apply for this exciting role.

  • Bachelor's degree in Science, Engineering, or a closely related field
  • Strong background in system verilog and OVM/UVM based constrained random verification
  • Experience with developing verification components/UVCs and testbenches for RTL verification
  • Proficient in low power SoC design constructs
  • 3+ years of hands-on experience in system verilog and OVM/UVM based constrained random verification
  • 3+ years in design validation/post-silicon debug
  • Experience with UPF based Power Aware verification
  • Functional coverage model development and code coverage closure
  • Desirable skills: proficiency in scripting languages and experience with Synopsys NLP tool

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