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3 days ago
This position involves leading the development of Digital Back End Engineers that enable customers to implement design with Cadence tools.
Key Responsibilities- Understanding of Digital microarchitecture definition and documentation
- Understanding of RTL logic design, debug and functional verification
- Understanding of IP integration and verification
- Understanding of digital architecture trade-offs for power, performance, and area
- Understanding of proper handling of multiple asynchronous clock domains and their crossings
- Understanding of synthesis timing constraints, static timing analysis and constraint development
- Understanding of fundamental physical design flows, e.g. floor planning and clock tree synthesis
- Understanding of the impacts of Analog and mixed-signal design and verification on digital-on-top development flow.
- Understanding of functional ECO flow and conformal ECO
- Experience with FPGA and/or emulation platform
- Firmware development of embedded microcontroller systems is a plus.
- Substantial experience with Verilog is required, as are excellent logic and debug skills.
- Minimum 5 years of ASIC backend design experience.
- Must have gone through successful tapeouts in advance technology nodes
- Be self-motivated and well organized.
Benefits
Main Expectations from Candidate
- Candidate must demonstrate significant expertise in advanced technologies.
- Candidate should be able to provide effective leadership and guidance to team members.
- Candidate must showcase innovative problem-solving skills and ability to collaborate across departments.
Working Details
The ideal candidate will work effectively within a cross-functional environment. This includes being able to manage time effectively and stay up-to-date with industry trends. Candidates who possess these traits will greatly contribute to our ongoing success.
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