Advanced ASIC Design Verification Expert

3 days ago

Cork, Cork, Ireland beBeeRtl Full time €90,000 - €120,000
Job Summary

An exciting opportunity has arisen for a talented ASIC Design Verification Engineer to join our team in Cork. As a key member of our engineering team, you will be responsible for developing and implementing verification methodologies, creating testbenches, and verifying sensor algorithm RTL for ASIC tapeout quality delivery.

About the Role
  • Deploy industry-leading verification methodologies such as UVM and Formal Verification.
  • Develop testbenches and verification components, including UVCs, C models, and reusable verification environments.
  • Verify sensor algorithm RTL for ASIC tapeout quality delivery.
  • Develop test plans based on design documents and interaction with design/systems engineers.
  • Implement C model integration within the UVM framework.
  • Write SystemVerilog assertions.
  • Debug, verify, optimize, and perform bit-exact matching with test vectors.
  • Analyze coverage data and collaborate with design teams to address coverage holes.
  • Develop and augment frameworks for running regressions.
  • Debug regression failures with design/systems teams.
  • Automate workflows and improve team efficiency using Python.
Requirements
  • Bachelor's degree in Science, Engineering, or a related field.
  • 3+ years of experience in ASIC design verification, UVM-based functional verification, or a related field.
  • Experience with constrained-random verification environments and UVM flow build-up, including Coverage-Driven verification methodology.
  • Proficiency in SystemVerilog Assertions.
  • Experience debugging test failures and reporting verification results to achieve coverage goals.
  • Extensive experience using RTL simulation tools.
  • Strong UVM, SystemVerilog, and Perl/Python shell-scripting skills.
  • Familiarity with C/C++.
  • Strong analytical skills and the ability to thrive in a dynamic, fast-paced team environment.
  • Excellent written and verbal communication skills and strong interpersonal skills.
Benefits
  • Visa support for candidates 4 years post-education.
  • Relocation assistance.
Preferred Qualifications
  • Experience using formal verification tools (e.g., Jasper, VC_Formal).
  • Experience with SystemC and Matlab.
  • Experience with gate-level simulation debug and power extraction tools.

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