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Senior ASIC Design Verification Engineer

2 weeks ago

Dublin, Dublin City, Ireland beBee Careers Full time
Senior ASIC Verification Engineer

We are looking for an experienced Senior ASIC Verification Engineer to join our team in Dublin. As a key member of our team, you will be responsible for developing and maintaining high-quality verification environments for complex digital designs.

Key responsibilities include designing and implementing SystemVerilog – UVM testbenches, developing UVC components from scratch for new verification environments, defining and writing functional coverage models, and debugging failing test cases. You will also participate in reviews to ensure test benches meet quality and completeness standards.

To succeed in this role, you will need a strong background in digital logic design and verification, as well as excellent problem-solving skills and the ability to work independently. In addition, you should have at least 8 years of experience in verification working with Verilog and/or SystemVerilog, and 5 years of experience on IP/block level Test-bench bring up on SV UVM based platforms. Familiarity with CAD/EDA tools for design and simulation, as well as working knowledge in scripting languages (such as Python, Perl, or TCL) is also required.