Mixed Signal Design/Verification Engineer
1 day ago
Mixed Signal Design/Verification Engineer, Cork
Client:
Location:
Cork, Ireland
Job Category:
Other
EU work permit required:
Yes
Job Reference:
ee1607f6a655
Job Views:
4
Posted:
Expiry Date:
Job Description:
About Analog Devices
Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible.
Learn more at and on.
Responsibilities Will Include:
UVM-based Design Verification of Digital & Mixed-Signal IP Blocks
Collaborate with analog and digital design teams to verify RTL and Analog/Mixed-Signal IP blocks in a system-level verification environment.
Design verification and DFT strategy development in interaction with architecture, design, physical design, software, and test teams.
Skills And Experience:
Bachelor's degree in electronic engineering or related field.
Solid understanding of analog and digital design principles, capable of describing circuit behavior and functionality.
Experience with circuit simulation in spice simulators, schematic debugging, waveform plotting, and analysis.
Proficiency in coding with Verilog or SystemVerilog and using digital simulators for verification.
Experience with mixed-signal test benches, SVA, functional coverage, constrained randomization, and UPF.
Knowledge of modeling HDL such as Verilog-AMS; SV-RNM is highly desirable, and UVM knowledge is a plus.
Experience with pre- and post-silicon verification workflows, automated test benches, and post-silicon ATE/PTE vector bringup and bench characterization.
Familiarity with test plan development, coverage analysis, transaction-level modeling, constrained random verification, assertion-based, and formal verification techniques using SystemVerilog.
Proficiency with Verilog, SystemVerilog, Assertions, and scripting languages like Python, TCL, Perl, or shell scripting.
Experience in analog mixed-signal verification techniques is advantageous.
Minimum Qualifications:
Bachelor's degree in science, engineering, or a related field.
At least 3 years of experience in design verification or related fields.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
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