Senior Verification Engineer
1 month ago
Responsibilities
- Collaborate with the design and architecture teams to develop and implement verification strategies
- Define and develop the verification architecture
- Use UVM methodology for testbench architecture and environment development
- Drive metric-driven verification methodologies to ensure comprehensive verification coverage
- Perform formal verification to guarantee the correctness of designs
- Contribute to Verilog RTL design and ensure it meets verification requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- Proven experience in verification engineering, particularly in IP development
- Proficiency in Verification architecture and UVM methodology
- Strong understanding of metric-driven verification
- Familiarity with formal verification techniques
- Hands-on experience in Verilog RTL design
- Collaborate with cross-functional teams to define verification strategies
- Develop and maintain verification environments using UVM
- Create and execute test plans to ensure comprehensive coverage
- Analyze and debug failures, and work with the design team to drive issue resolutions
- Continuously contribute to process improvement and mentor junior team members
For more information, please contact Rachel Mason at IC Resources.
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