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Asic Physical Design, Senior Staff Engineer

4 months ago

Dublin, Dublin City, Ireland Synopsys, Inc. Full time
Everything you need to enable innovation from Silicon to Software is what we make at Synopsys.


We're proud to be at the heart of the innovations that impact the world and change the way people live.


This opportunity offers much more than just an engineering job, this is from Synopsys Solution Group - the top IP provider in the world, where the best IPs with the broadest portfolio and the most advanced technology are created.


If you're ready to excel, innovate, and pursue a passion in ASIC physical design for IP, Subsystem or So C, we'd like to welcome you to our Digital Implementation team in Dublin.

L ocation in Ireland is flexible for the right candidates.

Preference is office based in Dublin but its not the only option.


With your expertise, together with the industry's most talented professionals in the team, empowered by Synopsys EDA ecosystem, you are fueling the new era of Smart Everything by offering high-speed silicon-proven interface IP solutions in the latest process technology for the most cutting-edge industry vertical including Artificial intelligence, Autonomous Vehicles, High-Performance Compute, Cloud, 5 G Mobile and the Io T etc.


IPs and subsystems you make will be integrated into tens of millions of So Cs that are used by billions of people.

You will be joining a true global team that has personality, enthusiasm and a fun culture with diversity.

You will have all the support you need to grow and develop with us.


No matter where you are in your career, the experience and expertise you grow here will put you miles ahead in the career advancement and open the path to all possibilities.

What You'll Be Doing Develop a variety of advanced high-performance interface IPs, test chips and subsystem (e.g.

Serdes/DDR/HDMI/MIPI/USB etc.) at the latest 7nm/5nm/3nm process nodes.


Drive the complete digital implementation from RTL to GDS including Synthesis, Floor Planning, Power Analysis and Planning, CTS, Placement and Routing, STA, EMIR Signoff and Physical Verification.

Create physical design methodologies and automation scripts for various implementation steps by leveraging Synopsys EDA ecosystem.


Ensure timely incoming and outgoing deliveries, report on project progress, interact and collaborate with multiple cross functional teams and the product team, and provide technical support to customers when needed.

What you'll bring in A relevant degree in Electrical or Computer Engineering, or Computer Science.

8+ years of hands-on experience in ASIC physical implementation and EDA tools.

Solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design.

Knowledge of industry standard data file formats: Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPM, CMM.

Scripting and programming skills:
TCL, Make, Unix Shell, Perl, Python.

Good written and verbal communication in English.

It would be amazing if you have Recent contribution to project tape-outs.

Understanding of logical bottle necks impacting timing closure and methods to overcome these challenges.

Proficiency in TCL, Make, Unix Shell, Perl, Python scripting.

Experience with Synopsys tools such as Design Compiler, IC Compiler (2), Fusion Compiler, Prime Time, IC Validator.

At Synopsys, we're at the heart of the innovations that change the way we work and play.

Self-driving cars.

Artificial Intelligence.

The cloud.
5 G.
The Internet of Things.

These breakthroughs are ushering in the Era of Smart Everything.

And we're powering it all with the world's most advanced technologies for chip design and software security.

If you share our passion for innovation, we want to meet you.

Stay Connected:
Join our Talent Community Inclusion and Diversity are important to us.


Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.