Senior Staff Verification Engineer

Senior Staff Verification Engineer page is loaded## Senior Staff Verification Engineerlocations: Cork, IEtime type: Full timeposted on: Posted Todayjob requisition id: JR-9142The Test & Characterization Engineering team provides value add by: Planning, carrying out or supporting the execution of test and approval procedures prescribed by agreed specifications or regulations.
Defining measuring and tests equipment, and designs test sequences and test instructions.
Preparing and processing testing sequences, ensuring result documentation and evaluating test results.
Verifying and documenting the characterization of products.
Cooperating with Engineers in Product Design and IE, and also with customers to testify best-in-class quality, product safety and regulatory compliance of products.
A job at this level: Applies function-specific engineering know how, methods, tools and principles on a range of technical subjects.
Initiates and oversees implementation, operations and service level of infrastructure (e. g. applications, systems, processes or services).
Takes over in-depth analysis of deficiencies/incidents and derives concepts for remediation, improvement projects or investments.
Supports stakeholder and counsel management how best utilize the infrastructure systems and services, and how to adapt service level.
Provides guidance to operational staff, and trains and oversees effective utilization of systems, tools, guidelines and procedures.
**Senior Staff Verification Engineer** for our IC product line.
**Responsible for:** As a Sr.
Staff Verification Engineer, you will contribute to the success of Vishay by working together with design, firmware and hardware emulation teams to ensure that Vishay's proprietary power devices are verified for performance, completeness and correctness.
**Job Location:**This position is located Cork, Ireland.
Other locations may also be considered.
**What you will be doing:*** Architecture of Verification Environments for block, subsystem, and SoC level designs.
* Development of UVM-SV Scoreboards for self-checking regressions.
* Development of Functional Coverage items like Covergroups and Corverpoints as part of Metric Driven Verification Environments.
* Development of SystemVerilog Assertions for use in Simulation Environments.
* Definition and Management of Verification Plans (vPlans) using Cadence vManager tools.
* Creation and Management of Automated Regression Environments.
* Verification scope will encompass analog, digital, and firmware functions as well as evaluation and benchmarking of full system performance.
* Work closely with analog designers, digital designers, systems architecture, firmware, applications, and test engineering to specify, design, develop, and manage a verification system for SOC.
* Knowledge of protocol interfaces for spec compliance (PMBus, SVI, SVID, I2C, AHB etc.).
* Track and report progress of the projects against key milestones.
* Provide an environment where collaboration, effective communication, and learning are fun and rewarding.You will have a comprehensive, demonstrable background in power semiconductors / semiconductor physics and/or electronics engineering.
You will approach tasks in a logic-based way, along with having the ability and motivation to develop novel and creative ideas.
Your communication skills will enable seamless collaboration both with our manufacturing partners and internally, and you will know how to build and maintain lasting relationships in international and cross-functional project teams.
**What you will bring along:*** PhD, post-graduate or degree qualification in Electronic Engineering or similar.
* 10+ years' relevant engineering experience.
* Experience of full-product verification flows, including HW & FW.
* Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology* Experienced with Assertions like System Verilog Assertions* Experience with vManager, vPlan and Regressions, etc.
* Experience working on mixed-signal ICs is a plus.
* Experience with debugging test failures and report verification result to achieve the expected functional/code coverage goals* Extensive usage of RTL simulation tools.
* UVM, System Verilog, Perl/Python shell-scripting skills required* Excellent interpersonal and communications skills.
* The ability to work with cross-functional teams.
* The ability to support and mentor less experienced team members**What can we offer you for your talent:**Vishay offers a comprehensive suite of benefit programs including health care coverage, financial support programs and other resources designed to help you achieve your personal and professional goals.
With us, you'll experience unique career paths, an open and collaborative culture, a stable business that will be there for you, and opportunities to work globally and locally.Vishay helps the world's most in-demand technologies come to life.
Every day our products touch your life and the lives of people across the world, though you likely do not know it.
Since 1962, we have defined what technology can be through our electronic components—we can also help you define your future.
With us, you'll experience unique career paths, an open and collaborative culture, a stable business that will be there for you, and opportunities to work globally and locally.
Come join us and help us build the DNA of tech.
### Building your experience.Along with the freedom and support to build your unique career, comes responsibility.
Career advancement is earned, not given, at Vishay.Some of the attributes of successful Vishay employees include:* Self-driven and hardworking* Intellectually and culturally flexible, curious and eager to learn* Excited to give, and receive, a challenge* Have strong integrity & ethics* Thrive in a teamwork environmentWe welcome you to identify new opportunities, take chances, and show your ability—speaking up and stepping up will open doors to leadership, cross-team, cross-functional, and cross-border experiences that will define and redefine your development.
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