Senior Principal Logic Design Engineer

1 week ago

Cork, Cork, Ireland Software Placements Full time

Client:
Our client a leading Multinational Semiconductor EDA Software provider requires
Senior Principal SoC Logic Design Engineer
for role based in
Cork City, Ireland
.
Role:
You will join a team implementing reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high- performance applications.
This is a technically rewarding role with high visibility within the organisation.
The team is responsible for supporting customers.
The group will also develop software and applications for reference systems and product demonstrations, highlighting the capability of subsystems and components.
This role requires extensive experience
IP integration, and in designing and implementing SoC and compute-based systems
.
You will work closely with compute and interface IP development engineering and build designs to demonstrate the capabilities of subsystems and components.
Responsibilities
:
Design, develop and debug SoC reference systems.
Integrate compute, memory and interface IP in system designs.
Analyse IP products and implementation flows.
Identify gaps and work with development teams to improve products.
Develop collateral, and training material for CSG system customers.
Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.
Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team's workflows.
Experience:
BS in Electronic Engineering/Computer Science with 15+ years work experience, or MS in EE/CS with 8+ years experience.
Must have at least 4 years of experience in ASIC design, integration, or verification teams.
Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.
Expertise in Verilog/System Verilog for coding and verification.
Proficiency in RTL design techniques, including synthesis, timing closure, and verification.
Experience in using UVM for functional verification of ASIC designs.
Experience with EDA tools like Cadence and Synopsys for design simulation and verification.
Extensive experience with FPGA emulation, design tools, and verification.
Contact:
For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email
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