DFT Architect/Lead Engineer- Test

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Microchip's fast-growing Analog Power and Interface Division (APID) is looking for an experienced and motivated Design-For-Test (DFT) Architect/Lead Engineer to participate in a talented test architecture team to define and implement best DFT practices to help make designs more easily testable, more cost effective and provide reusable building blocks that can be used for multiple semiconductor device test applications. As a senior technical member of the test development team you will also be responsible to help mentor and train junior test engineering staff and actively participate in key test strategic decisions.

The candidate should be self-driven, motivated and capable of embracing a fast paced, continuously evolving and improving culture. Experience in all stages of new product test development and DFT methodologies are critical to this position and special consideration will be given to candidates who have had experience in mentoring and leading junior engineers as a technical team leader. The candidate should have excellent communication skills which are required to span across global teams and shared test applications within Microchip.

Responsibilities:

• Perform detailed review of design objective specifications (DOS) and evaluate/define design for testability (DFT) features.
• Utilize experience in DFT implementation for analog and mixed-signal testing methodologies.
• Provide technical leadership for developing DFT architectures.
• Accompany design projects starting from DOS phase 0.3 (early project definition phase) until RTP (release to production).
• Work in close collaboration with various product line teams including design, test, applications and product engineering.
• Define DFT requirements and write detailed DFT manuals to be used by design and test team members.
• Match parameters from Electrical Characteristics table in DOS with critical ATE testing parameters and methods.
• Apply knowledge of ATE tester instruments and measurement specifications.
• Employ knowledge of ATE load board restrictions including layout and key testing requirements & accuracies.
• Cooperate with worldwide cross-functional teams (marketing, application, design, layout, lab and test engineers).

Minimum Requirements:

• A university degree in Electrical or Computer Engineering with 10+ years experience developing ATE analog/mixed-signal test solutions including DFT applications.
• Analog design experience/exposure required for close development of DFT IP blocks, ability to read schematics and understand circuit needs and tradeoffs.
• Experience mentoring junior engineers and staff.
• Experience with analog and mixed-signal ATE platforms (ex: Eagle, Teradyne, SPEA).
• Must possess an in-depth knowledge of analog, power and mixed-signal device theory and test methodology.
• Understand block diagrams of analog blocks like buck/boost regulators, linear regulators, PMIC's, ADC's, USB and motor power delivery circuits.
• Understand device behavior and modes in terms of observability and controllability using different test conditions and possible impact on ATE tests.
• Have experience with Cadence Virtuoso or similar tool and ability to read design circuit schematics.
• Experience with analog, power and mixed signal PCB design and layout (ex: Altium Designer).
• Strong analytical and problem-solving skills with an understanding of semiconductor test and FA methods.
• Must possess excellent communication skills and ability to work in a global multi-functional team environment.
• Strong team player and open-minded.

Highly Desired Skills:

• Experience on analog and mixed-signal ATE platforms: SPEA C600/DOT800, LTX Fusion EX, ETS-300/88/364.
• Understanding of DFT, BIST, SCAN, statistical process control, calibration theory, and test limit guard banding methodology.
• Generation of detailed Test Specifications from Device Specifications.
• Conducting comprehensive Test Plan Reviews and Peer Reviews.
• Experience leading a small test team or directly responsible for mentoring/overseeing junior staff.