
Senior Verification Specialist
1 week ago
The ideal candidate will be responsible for collaborating with cross-functional teams to ensure the successful verification of complex systems. They will develop and execute detailed test plans, design verification environments, and debug issues to ensure system performance meets expectations.
- Develop detailed test and coverage plans based on architecture and micro-architecture.
- Design verification environments in SystemVerilog/UVM/SystemC/C++.
- Execute verification plans, including design bring-up, DV environment bring-up, regression, and debug of test failures.
- Identify, isolate, and debug verification issues, driving resolution with design and architecture teams.
The ideal candidate will have a Master's degree in a relevant field and minimum 15 years of experience in verification of complex SoC or IP. Strong debugging and problem-solving skills are necessary for success in this role.
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Staff Mixed-Signal Dv Engineer
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