Senior Power Verification Engineer

6 days ago

Cork, Cork, Ireland beBeeVerification Full time €96,000 - €124,000

Join a leading Multinational Semiconductor PMIC Company in Ireland. Our client requires a Senior Staff Verification Engineer to work onsite at least 3 days per week.

The role contributes to the success of the company by working together with design, firmware and hardware emulation teams to ensure that proprietary power devices are verified for performance, completeness and correctness.

Key Responsibilities:

  1. Design and develop verification environments for block, subsystem, and SoC level designs.
  2. Develop UVM-SV Scoreboards for self-checking regressions.
  3. Develop Functional Coverage items like Covergroups and Corverpoints as part of Metric Driven Verification Environments.
  4. Develop SystemVerilog Assertions for use in Simulation Environments.
  5. Define and manage Verification Plans using Cadence vManager tools.
  6. Create and manage Automated Regression Environments.
  7. Verify analog, digital, and firmware functions, as well as evaluate and benchmark full system performance.
  8. Collaborate with cross-functional teams to specify, design, develop, and manage a verification system for SOC.
  9. Knowledge of protocol interfaces for spec compliance (PMBus, SVI, SVID, I2C, AHB etc.).
  10. Track and report progress against key milestones.
  11. Provide an environment where collaboration, effective communication, and learning are rewarding.
  12. A comprehensive background in power semiconductors / semiconductor physics and/or electronics engineering is required.
  13. You will approach tasks in a logic-based way, along with having the ability and motivation to develop novel ideas.
  14. Your communication skills will enable seamless collaboration both with our partners and internally, and you will know how to build lasting relationships in international project teams.

Requirements:

  1. PhD, post-graduate or degree qualification in Electronic Engineering or similar.
  2. 10+ years' relevant engineering experience.
  3. Experience of full-product verification flows, including HW & FW.
  4. Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology.
  5. Experienced with Assertions like System Verilog Assertions.
  6. Experience with vManager, vPlan and Regressions, etc.
  7. Experience working on mixed-signal ICs is a plus.
  8. Extensive usage of RTL simulation tools.
  9. UVM, System Verilog, Perl/Python shell-scripting skills required.
  10. Excellent interpersonal and communications skills.

We Offer:

This is a challenging role for someone who enjoys working with complex technical projects and has excellent problem-solving skills. If you are looking for a new challenge, apply now.

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