Mixed Signal Design/Verification Engineer

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Mixed Signal Design/Verification Engineer, Limerick
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Client:
Location:
Limerick, Ireland
Job Category:
Other
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EU work permit required:
Yes
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Job Reference:
6b f
Job Views:
5
Posted:

Expiry Date:

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Job Description:
About Analog Devices
Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible.
Learn more atand onand.
Responsibilities Will Include:
UVM based Design Verification of Digital & Mixed-Signal IP Blocks
Work closely with analog and digital design teams to verify RTL and Analog/Mixed-Signal IP blocks in a system level verification environment.
Interact with architecture, design, physical design, software, design evaluation and test teams to design suitable verification and DFT strategies.
Skills And Experience
Bachelor's degree in electronic engineering or related field.
Solid understanding of basics of analog and digital design,
able to describe circuit behavior and functionality
Experience in simulating circuits in spice simulators, debugging schematics, plotting and analyzing waveforms
Demonstrated ability to read and write code in Verilog or System Verilog
, use of digital simulators for verifying simple designs
Work experience with
mixed-signal test benches, SVA, functional coverage, constrained randomization and UPF
Knowledge of any HDL for modeling such as
Verilog-AMS; SV-RNM is highly desirable, UVM knowledge is a plus
Experience of pre and post-silicon verification testflow and automated test benches.
Post silicon ATE/PTE vector bringup and bench characterization support.
Knowledge of test-plan development, coverage (code/functional) analysis, transaction level modelling, constrained random verification, assertion based and formal verification techniques with System Verilog
Experience with Verilog, System Verilog, Assertions, Python/TCL/Perl/shell-scripting.
Experience in analog mixed signal verification techniques will be a plus.
Minimum Qualifications:
Bachelor's degree in science, Engineering, or related field.
3+ years design verification, or related work experience.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
About Analog Devices
Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.
ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world.
With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible.
Learn more atand onand.
Responsibilities Will Include:
UVM based Design Verification of Digital & Mixed-Signal IP Blocks
Work closely with analog and digital design teams to verify RTL and Analog/Mixed-Signal IP blocks in a system level verification environment.
Interact with architecture, design, physical design, software, design evaluation and test teams to design suitable verification and DFT strategies.
Skills And Experience
Bachelor's degree in electronic engineering or related field.
Solid understanding of basics of analog and digital design,
able to describe circuit behavior and functionality
Experience in simulating circuits in spice simulators, debugging schematics, plotting and analyzing waveforms
Demonstrated ability to read and write code in Verilog or System Verilog
, use of digital simulators for verifying simple designs
Work experience with
mixed-signal test benches, SVA, functional coverage, constrained randomization and UPF
Knowledge of any HDL for modeling such as
Verilog-AMS; SV-RNM is highly desirable, UVM knowledge is a plus
Experience of pre and post-silicon verification testflow and automated test benches.
Post silicon ATE/PTE vector bringup and bench characterization support.
Knowledge of test-plan development, coverage (code/functional) analysis, transaction level modelling, constrained random verification, assertion based and formal verification techniques with System Verilog
Experience with Verilog, System Verilog, Assertions, Python/TCL/Perl/shell-scripting.
Experience in analog mixed signal verification techniques will be a plus.
Excellent communication skills
Minimum Qualifications:
Bachelor's degree in science, Engineering, or related field.
3+ years design verification, or related work experience.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days #J-18808-Ljbffr